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semiconductor technical data order number: MPC9990/d rev 4, 01/2002 ? motorola, inc. 2002

the MPC9990 is a low voltage pll clock driver designed for high speed clock generation and distribution in high performance computer, workstation and server applications. the clock driver accepts a lvpecl compatible clock signal and provides 10 low skew, differential hstl 1 compatible outputs, one hstl compatible output for system synchronization purposes and one hstl compatible pll feedback output. the device operates from a dual voltage supply: 3.3 v for the core logic and 1.8 v for the hstl outputs. the fully integrated pll supports an input frequency range of 75 to 287.5 mhz. the output frequencies are configurable. ? supports high performance hstl clock distribution systems ? compatible to ia64 processor systems ? fully integrated pll, differential design ? core logic operates from 3.3 v power supply ? hstl outputs operate from a 1.8 v supply ? programmable frequency by output bank ? 10 hstl compatible outputs (two banks) ? hstl compatible pll feedback output ? hstl compatible sychronization output (qsync) ? max. skew of 80 ps within output bank ? zerodelay capability: max. spo (tpd) window of 150 ps ? lvpecl compatible clock input, lvcmos compatible control inputs ? temperature range of 0 to +70 c the MPC9990 provides output clock frequencies required for highperformance computer system optimization. the device drives up to 10 differential clock loads within the frequency range of 75 to 287.5 mhz. the 10 outputs are organized in 2 banks of 3 and 7 differential outputs. in the standard configuration the qfb output pair is connected to the fb input pair closing the p ll loop and enabling zero delay operation from the clk input to the outputs. bank b outputs are frequency and phase aligned to the clk input, providing exact copies of the highspeed input signal. bank a outputs are configured to operate at slower speeds driving the system bus devices. the output frequency ratio of bank a to bank b is adjustable (for available ratios, see ampc999 0 application: cpu to system bus frequency ratioso on page 2) for system optimization. in a computer application, bank b outputs generate the clock signals for the devices operating at the cpu frequency, while bank a outputs are configured to drive the clock signals for the devices running at lower speeds (system clock). four individual frequency ratios are available, provi ding a high degree of flexibility. the frequency ratios between cpu clock and system clock provided by the MPC9990 are listed in the table aoutput configurationo on page 4. the qsync output functionality is designed for system synchronization purpose. qsync is asserted at coincident rising edges of cpu (bank b and qfb signal) and slower system clock (bank a) outputs (see aqsync phase relation diagramo on page 4), providing baseline timing in systems with fractional clocks. the qsync output is asserted for one qfb high pulse, centered on the rising qfb output. figure 1. MPC9990 application example MPC9990 250 mhz qfb fb qsync qb[0:2] clk qa[0:6] 250 mhz cpu clocks system clocks: 250, 200, 187, 125 mhz system synchronization 1. in order to minimize outputtooutput skew, hstl outputs of the MPC9990 are generated with an open emitter architecture. for output termination, see ohstl output termination and ac test referenceo on page 5. this document contains information on a product under development. motorola reserves the right to change or discontinue this pr oduct without notice.
low voltage differential peclhstl pll clock driver fa suffix 48lead lqfp package case 932
MPC9990 motorola timing solutions 2 figure 2. MPC9990 logic diagram vco clk clk fb fb qa0 qa0 qa1 qa1 qa2 qa2 qa3 qa3 qa4 qa4 qa5 qa5 qa6 qa6 qb0 qb0 qb1 qb1 qb2 qb2 qfb qfb qsync qsync oe asel[0:1] test bsel lpf pd qsync pulse control bank b bank a test mode control data generator vco_sel mr table 1: MPC9990 application: cpu to system bus frequency ratios qa to qb frequency ratio 1:1 1:2 3:4 4:5 output frequencies for clk = 75 mhz (bsel=1, vco_sel=1) qa output frequency 75 37.5 56.25 60 mhz qb output frequency 75 75 75 75 mhz output frequencies for clk = 100 mhz (bsel=1, vco_sel=1) qa output frequency 100 50 75 80 mhz qb output frequency 100 100 100 100 mhz output frequencies for clk = 125 mhz (bsel=1, vco_sel=1) qa output frequency 125 62.5 93.75 100 mhz qb output frequency 125 125 125 125 mhz output frequencies for clk = 150 mhz (bsel=1, vco_sel=0) qa output frequency 150 75 112.5 120 mhz qb output frequency 150 150 150 150 mhz output frequencies for clk = 200 mhz (bsel=1, vco_sel=0) qa output frequency 200 100 150 160 mhz qb output frequency 200 200 200 200 mhz output frequencies for clk = 250 mhz (bsel=1 vco_sel=0) qa output frequency 250 125 187.5 200 mhz qb output frequency 250 250 250 250 mhz
MPC9990 timing solutions 3 motorola fb qfb qfb vcco qb0 qb0 qb1 qb1 vcco qb2 qb2 fb vcco qa3 qa3 qa4 qa4 vcco vcc qa5 qa5 qa6 qa6 vcco bsel vcc gnd asel [0] asel [1] vco_sel test mr clk clk 37 38 39 40 41 42 43 44 45 46 47 48 24 23 22 21 20 19 18 17 16 15 14 13 123456789101112 36 35 34 33 32 31 30 29 28 27 26 25 MPC9990 oe gnd vcca gnd qsync qsync vcco qa0 qa0 qa1 qa1 vcco qa2 qa2 figure 3. 48lead package pinout (top view) table 2: pin configuration pin i/o type internal resistor description clk, clk input lvpecl clk: pull-down, clk : pull-up differential clock frequency input fb, fb input hstll fb: pull-down, fb : pull-up differential feedback input qan, qan output hstl bank a outputs qbn, qbn output hstl bank b outputs qsync, qsync output hstl synchronization output qfb, qfb output hstl differential feedback output vco_sel input lvcmos pull-down selection of operating frequency range asel[0:1] input lvcmos pull-down selection of bank a output frequency bsel input lvcmos pull-down selection of bank b output frequency test input lvcmos pull-down selection of pll operation or test mode (pll bypass) mr input lvcmos pull-up master reset. assertion of master reset required on startup oe input lvcmos pull-up output enable v cca power supply analog power supply, typical 3.3 v v cc power supply core power supply, typical 3.3 v v cco power supply output power supply, typical 1.8 v gnd ground output, analog and core logic ground, 0v (vee)
MPC9990 motorola timing solutions 4 table 3: output frequency relationship for an example configuration asel[0] asel[1] bsel f qan f qbn f qfb qsync 0 0 0 clk clk clk l 0 1 0 clk 2 clk 2 clk enabled 1 0 0 clk x 3 4 clk x 3 4 clk enabled 1 1 0 clk x 4 5 clk x 4 5 clk enabled 0 0 1 clk clk clk l 0 1 1 clk 2 clk clk enabled 1 0 1 clk x 3 4 clk clk enabled 1 1 1 clk x 4 5 clk clk enabled table 4: function table (controls) control pin 0 1 test pll enabled pll bypassed (static test mode) mr reset (internal logic and pll) normal operation mode oe outputs disabled (q x = l, q x = h), except qfb, qfb outputs enabled vco_sel high frequency operation (vco frequency range from 600 to 1150 mhz) low frequency operation (vco frequency range from 300 to 575 mhz) figure 4. qsync phase relation diagram qax qfb qsync the MPC9990 has a system synchronization pulse output (qsync). the qsync pulse output is synchronous to the feedback clock signal (qfb) and activated when both qfb and bank a outputs are programmed to run at a frequency ratio other than 1:1. in the case of a 1:1 frequency ratio (asel[] = 00), qsync remains low. qsync output transitions occur prior coincident rising edges of qfb and bank a. the pulse width of the qsync pulse is equal to the period of the feedback clock frequency (qfb). the qsync pulse is asserted at the last falling edge of qfb prior to the coincident edge event, and deasserted at the next falling edge of qfb (see aqsync phase relation diagramo). if bsel = 1 and the pll is frequency and phase-locked, qsync pulses occur on coincident edges between the qa-bank and qb-bank outputs (offset by feedback delay) due to the fixed phase relation between clk, qfb and qb-bank outputs. table 5: absolute maximum ratings* symbol characteristics min max units condition v cca analog power supply 0.5 3.6 v v cc core power supply 0.5 3.6 v v cco output power supply 0.5 3.6 v v in input voltage 0.5 v cc + 0.3 v i in input current 1.0 1.0 ma dc i out output current 50 50 ma dc t s storage temperature 50 150 c * absolute maximum continuous ratings are those values beyond which damage to the device may occur. exposure to these conditions or conditions beyond those indicated may adversely affect device reliability. functional operation at absolutemaximumrated condi tions is not implied.
MPC9990 timing solutions 5 motorola table 6: dc characteristics (v cc = v cca = 3.3 v 5%, v cco = 1.7 to 2.1v, t a = 0 to 70 c) symbol characteristics 0 c 25 c 70 c unit condition min typ max min typ max min typ max hstl i/o a v cco output power supply 1.7 1.8 2.1 1.7 1.8 2.1 1.7 1.8 2.1 v in input voltage (fb) -0.3 1.45 -0.3 1.45 -0.3 1.45 v differential v dif differential input voltage b (fb) 0.2 1.75 0.2 1.75 0.2 1.75 v differential v cm common mode input voltage c (fb) 0.64 0.9 0.68 0.9 0.68 1.0 v v oh output high voltage 1.0 v x +0.4 1.4 1.0 v x +0.4 1.4 1.0 v x +0.4 1.4 v v ol output low voltage 0 v x -0.4 0.4 0 v x -0.4 0.4 0 v x -0.4 0.4 v lvpecl i/o v cc power supply voltage (core) 3.135 3.3 3.465 3.135 3.3 3.465 3.135 3.3 3.465 v v cca power supply voltage (pll) 3.135 3.3 3.465 3.135 3.3 3.465 3.135 3.3 3.465 v v pp peak-to-peak input voltage clk, pclk 500 1000 500 1000 500 1000 mv v cmr common mode range d clk, pclk v cc -1.4 v cc - 0.6 v cc -1.4 v cc - 0.6 v cc -1.4 v cc - 0.6 v i ih input high current 150 150 150 m a i cc power supply current (core) 400 400 400 ma i cca power supply current (pll) 15 20 15 20 15 20 ma lvcmos inputs v ih input high voltage 2 v cc 2 v cc 2 v cc v v il input low voltage 0 0.8 0 0.8 0 0.8 v i i input current 100 100 100 m a a. see ahstl differential input levelso. b. v dif specifies the input differential voltage. c. v cm is the maximum allowable range of v tr - ((v tr - v cp )/2). v tr is true input signal, v cp is its complementary input signal. d. v cmr is the difference from v cc and the crosspoint of the differential input signal. normal operation is obtained when the ahigho input is within the v cmr range and the input swing lies within the v pp specification. e. lvpecl input level specifications will vary 1:1 with v cc . figure 5. hstl differential input levels v cco v cmr v dif v tr v x v cp v ee figure 6. hstl output termination and ac test reference MPC9990 z = 50 w r t = 50 w v tt = gnd z = 50 w r t = 50 w v tt = gnd differential pulse generator z = 50
MPC9990 motorola timing solutions 6 table 7: ac characteristics (v cci = v cca = 3.3 v 5%, v cco = 1.7 to 2.1 v, t a = 0 to 70 c) a symbol characteristics 0 c 25 c 70 c unit condition min typ max min typ max min typ max f in input frequencyb for vco_sel = 0 (high range) 1:1 ratio, asel=00 1:2 ratio, asel=01 3:4 ratio, asel=10 4:5 ratio, asel=11 input frequency b for vco_sel = 1 (low range) 1:1 ratio, asel=00 1:2 ratio, asel=01 3:4 ratio, asel=10 4:5 ratio, asel=11 150.0 150.0 200.0 150.0 75.0 75.0 100.0 75.0 287.5 287.5 287.5 287.5 143.75 143.75 191.67 143.75 150.0 150.0 200.0 150.0 75.0 75.0 100.0 75.0 287.5 287.5 287.5 287.5 150.0 150.0 191.6 7 150.0 150.0 150.0 200.0 150.0 75.0 75.0 100.0 75.0 287.5 287.5 287.5 287.5 150.0 150.0 191.6 7 150.0 mhz mhz mhz mhz mhz mhz mhz mhz 600 < f vco < 1150 mhz 300 < f vco < 575 mhz f vco vco frequency vco_sel = 0 (high range) vco_sel = 1 (low range) 600 300 1150 575 600 300 1150 575 600 300 1150 575 mhz mhz f out output frequency c 287.5 287.5 287.5 mhz spo static phase offset, t pd between clk and fb vco_sel=0 vco_sel=1 -200 -250 -50 -50 -200 -250 -50 -50 -200 -250 -50 -50 ps ps dc output duty cycle 45 50 55 45 50 55 45 50 55 % t sk differential output skew t sk(ob) within bank d t sk(o) single frequency e t sk(o) multiple frequency f t sk(ofb) qfb to qa0-6 for asel=00 for asel=01 for asel=10 for asel=11 85 25 135 65 80 100 250 -115 -175 -115 -135 85 25 135 65 80 100 250 -115 -175 -115 -135 85 25 135 65 80 100 250 -115 -175 -115 -135 ps ps ps ps ps ps ps diff. hstl outputs v pp g minimum input swing 0.5 1 0.5 1 0.5 1 v lvpecl v cmr common mode range 1 v cc -0. 4 1 v cc -0 .4 1 v cc -0 .4 v lvpecl v dif,out minimum output swing 0.6 0.8 0.6 0.8 0.6 0.8 v hstl v x differential output crosspoint voltage 0.64 0.9 0.68 0.9 0.68 1.0 v hstl t jit(cc) cycle-to-cycle jitter f vco >= 750 mhz f vco < 750 mhz 75 125 75 125 75 125 ps ps t jit(per) period jitter vco_sel=0 vco_sel=1 75 125 75 125 75 125 ps ps t jit(io) i/o phase jitter rms (1 s ) 600 mhz< f vco <750 mhz 750 mhz< f vco <900 mhz 900 mhz< f vco <1150 mhz 50 40 30 50 40 30 50 40 30 ps ps ps bw pll bandwidth 1:1 ratio, asel=00 1:2 ratio, asel=01 3:4 ratio, asel=10 4:5 ratio, asel=11 0.6-1.0 0.6-1.0 1.0-1.2 0.6-1.0 0.6-1.0 0.6-1.0 1.0-1.2 0.6-1.0 0.6-1.0 0.6-1.0 1.0-1.2 0.6-1.0 mhz mhz mhz mhz t r , t f output transition rate 0.8 2 0.8 2 0.8 2 v/ns t lock pll lock time 10 10 10 ms a. refer to ahstl output termination and ac test referenceo for ac test conditions. b. the input frequency for the output configurations are limited by the vco frequency range and the feedback divider. c. f out at which output-to-output skew, v x and dc specification are still meet. f out is primary a function of f in and the input-to-output frequency ratio (m:n). d. output skew within bank a outputs (qa0-qa6) and output skew within bank b outputs (qb0-qb2). e. output skew within all outputs (qa0-qa6, qb0-qb2) running at the same output frequency. f. output skew within all outputs (qa0-qa6, qb0-qb2) running at any output frequency. g. v pp specifies the minimum input differential voltage required for switching.
MPC9990 timing solutions 7 motorola applications information using the MPC9990 in zero-delay applications nested clock trees are typical applications for the MPC9990 designs using the MPC9990 as pll fanout buffer with zero insertion delay will show significantly lower clock skew than clock distributions developed from static fanout buffers. the external feedback option of the MPC9990 clock driver allows for its use as a zero delay buffer. by using the differential qfb output pair as a feedback to the pll the propagation delay through the device is virtually eliminated. the pll aligns the feedback clock output edge with the clock input reference edge resulting a near zero delay through the device. the maximum insertion delay of the device in zero-delay applications is measured between the reference clock input (clk) and any output. this effective delay consists of the static phase offset (spo), i/o jitter (phase or long-term jitter), feedback path delay and the output-to-output skew error relative to the feedback output. calculation of part-to-part skew the MPC9990 zero delay buffer supports applications where critical clock signal timing can be maintained across several devices. if the reference clock inputs of two or more MPC9990 are connected together, the maximum overall timing uncertainty from the common clk input to any output is: t sk(pp) = t ( ? ) + t sk(o) + t pd, line(fb) + t jit( ? ) cf this maximum timing uncertainty consist of 4 components: static phase offset (spo), output skew, feedback board trace delay and i/o (phase) jitter. the output skew (t sk(o) ) specification of the MPC9990 is different for single or for dual frequency bank configurations. : figure 7. MPC9990 max. device-to-device skew t pd,line(fb) t jit( ? ) + t sk(o) t ( ? ) +t ( ? ) t jit( ? ) + t sk(o) t sk(pp) max. skew clk common fb device 1 any q device 1 fb device2 any q device 2 complementary signals are not shown. signal refer- ences level is the differential voltage crosspoint v x due to the statistical nature of i/o jitter a rms value (1 ) is specified. i/o jitter numbers for other confidence factors (cf) can be derived from table 8. table 8: confidence facter cf cf probability of clock edge within the distribution 1 0.68268948 2 0.95449988 3 0.99730007 4 0.99993663 5 0.99999943 6 0.99999999 the feedback trace delay is determined by the board layout and can be used to fine-tune the effective delay through each device. in the following example calculation a i/o jitter confidence factor of 99.7% ( 3 ) and single frequency configuration is assumed, resulting in a worst case timing uncertainty from input to any output of -420 ps to +170 ps relative to clk. t sk(pp) = [200ps...50ps] + [100ps...100ps] + [(30ps 3)...(30ps 3)] + t pd, line(fb) t sk(pp) = [420ps...+170ps] + t pd, line(fb) due to the frequency dependence of the i/o jitter, figure 8. amax. i/o jitter versus frequencyo can be used for a more precise timing performance analysis. the number for the i/o jitter at a specific frequency can be substituted for the more general datasheet specification number: figure 8. max. i/o jitter versus frequency
MPC9990 motorola timing solutions 8 power supply filtering the MPC9990 is a mixed analog/digital product. its analog circuitry is naturally susceptible to random noise, especially if this noise is seen on the power supply. random noise on the v cca power supply impacts the device ac characteristics, for instance i/o jitter. the MPC9990 provides separate power supplies for the output buffers (v cco ) and the phase-locked loop (v cca ) of the device. figure 9. recommended power supply filter r f 9 for v cc = 3.3v 2 7 place v cca filter and v cco , v cc bypass ca- pacitors as close as possible to the device v cca v cc v cco r f c f 6.8 m f 10 nf 33 ... 100 nf 33 ... 100 nf 3.3v 5% +0.3 v 0.1 v 1.8v MPC9990 the purpose of this design technique is to isolate the high switching noise digital outputs from the relatively sensitive internal analog phase-locked loop. in a digital system environment where it is difficult to minimize noise on the power supplies a second level of isolation may be required. a simple but effective form of isolation is a power supply filter on the v cca pin for the MPC9990. figure 9. illustrates a recommended power supply low-pass frequency filter scheme. the MPC9990 vco frequency and phase stability is most susceptible to noise with spectral content in the 300 khz to 3 mhz range. therefore the filter should be designed to target this range. the key parameter that needs to be met in the final filter design is the dc voltage drop across the series filter resistor r f . the maximum voltage drop on v cca that can be tolerated is 135 mv with respect to v cc = 3.3v 5%, resulting in a lowest allowable supply voltage for v cca equal to 2.835 v. from the data sheet the i cca current (the current sourced through the v cca pin) is typically 11 ma (15 ma maximum), assuming that the minimum of 3.0v (v cc =3.3v-5%-0.135v) must be maintained on the v cca pin. the resistor r f shown in figure 9. arecommended power supply filtero should have a maximum resistance of 9 to meet the voltage drop criteria. the minimum resistance for r f and the filter capacitor c f are defined by the required filter characteristics: the rc filter should provide an attenuation greater 40 db for noise whose spectral content is above 300 khz. in the example rc filter shown in figure 9. arecommended power supply filtero, the filter cut-off frequency is 16.3 khz and the noise attenuation at 300 khz is approximately 42 db. as the noise frequency crosses the series resonant point of an individual capacitor its overall impedance begins to look inductive and thus increases with increasing frequency. the parallel capacitor combination shown (6.8 m f || 10 nf) ensures that a low impedance path to ground exists for frequencies well above the bandwidth of the pll. although the MPC9990 has several design features to minimize the susceptibility to power supply noise (isolated power and grounds, internal voltage regulation and fully differential pll) there still may be applications in which overall performance is being degraded due to system power supply noise. the power supply filter schemes discussed in this section should be adequate to eliminate power supply noise related problems in most designs. recommended power-up sequence the MPC9990 does not require any special supply ramp sequence in case the system provides all supply voltages (3.3v and 1.8v) at the same time. the reference clock signal (clk, clk ) can be applied any time during or after the power up sequence if v in is smaller or equal v cc during the voltage transition. following are guidelines for the MPC9990 power-up sequence in case the 3.3v and 1.8v voltage supply cannot be applied at the same time: ? hstl output supply voltage v cco must be powered up to the specified voltage range before or at the same time than v cc . v cca can be powered up before, at the same time or after v cc and v cco . ? at the time the power supplies are powered up, the device should be reset (mr =0). ? apply the clock input signals to the pll (clk, clk ) after all power supplies are stable. then, mr can be deasserted (mr =1). this will release the internal pll which will attempt to lock ? the time from mr deassertion to pll lock will be specified by the pll lock time t lock. after the pll achieved lock, the ac characteristics are valid. ? outputs can be enabled by oe any time. qfb is not affected by oe and the pll can achieve lock even if oe is tied high (oe = 1, disable).
MPC9990 timing solutions 9 motorola figure 10. outputtooutput skew t sk(o) , t sk(ob) figure 11. propagation delay (t ? , static phase offset, spo) test reference figure 12. output duty cycle (dc) figure 13. i/o jitter the pintopin skew is defined as the worst case difference in propagation delay between any two similar delay path within a single device (t sk(o) ) or within a single output bank (t sk(ob) ) the time from the pll controlled edge to the non controlled edge, divided by the time between pll controlled edges, expressed as a percentage v x t sk(o) , t sk(ob) q x v x q x t p t 0 dc = t p /t 0 x 100% t ( ? ) t jit ?? ) = | t 0 t 1 mean | clk fb the deviation in t 0 for a controlled edge with respect to a t 0 mean in a random sample of cycles, measured at the fb signal (only true signal shown) q x q x q y q y v x v x clk clk fb fb v x v x v x clk figure 14. cycletocycle jitter figure 15. period jitter the variation in cycle time of a signal between adjacent cycles, over a random sample of adjacent cycle pairs, measured at an output (only true signal shown) the deviation in cycle time of a signal with respect to the ideal period over a random sample of cycles (only true signal shown) t n t jit(cc) = | t n t n+1 | t n+1 t jit(per) = | t n 1 / f 0 | t 0 t f t r v oh figure 16. output transition time test reference 80% 20% v ol
MPC9990 motorola timing solutions 10 outline dimensions fa suffix lqfp package case 932-03 issue f ??? ??? ??? a a1 z 0.200 ab tu 4x z 0.200 ac tu 4x b b1 1 12 13 24 25 36 37 48 s1 s v v1 p ae ae t, u, z detail y detail y base metal n j f d tu m 0.080 z ac section aeae ad g 0.080 ac m top & bottom l w k aa e c h 0.250 r 9 detail ad notes: 1. dimensioning and tolerancing per asme y14.5m, 1994. 2. controlling dimension: millimeter. 3.datum plane ab is located at bottom of lead and is coincident with the lead where the lead exits the plastic body at the bottom of the parting line. 4.datums t, u, and z to be determined at datum plane ab. 5.dimensions s and v to be determined at seating plane ac. 6.dimensions a and b do not include mold protrusion. allowable protrusion is 0.250 per side. dimensions a and b do include mold mismatch and are determined at datum plane ab. 7.dimension d does not include dambar protrusion. dambar protrusion shall not cause the d dimension to exceed 0.350. 8.minimum solder plate thickness shall be 0.0076. 9.exact shape of each corner is optional. t u z ab ac gauge plane dim a min max 7.000 bsc millimeters a1 3.500 bsc b 7.000 bsc b1 3.500 bsc c 1.400 1.600 d 0.170 0.270 e 1.350 1.450 f 0.170 0.230 g 0.500 bsc h 0.050 0.150 j 0.090 0.200 k 0.500 0.700 m 12 ref n 0.090 0.160 p 0.250 bsc l 0 7 r 0.150 0.250 s 9.000 bsc s1 4.500 bsc v 9.000 bsc v1 4.500 bsc w 0.200 ref aa 1.000 ref
MPC9990 timing solutions 11 motorola notes
MPC9990 motorola timing solutions 12 motorola reserves the right to make changes without further notice to any products herein. motorola makes no warranty, represe ntation or guarantee regarding the suitability of its products for any particular purpose, nor does motorola assume any liability arising out of the applicati on or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. atypicalo para meters which may be provided in motorola data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. all ope rating parameters, including atypicalso must be validated for each customer application by customer's technical experts. motorola does not convey any license under it s patent rights nor the rights of others. motorola products are not designed, intended, or authorized for use as components in systems intended for surgical imp lant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the motorola product cou ld create a situation where personal injury or death may occur. should buyer purchase or use motorola products for any such unintended or unauthorized application, buyer shall indemnify and hold motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expens es, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized u se, even if such claim alleges that motorola was negligent regarding the design or manufacture of the part. motorola, inc. motorola, inc. is an equal opportunity/a ffirmative action employer. motorola and the logo are registered in the us patent & trademark office. all other product or service names are the prop erty of their respective owners. motorola, inc. 2002. how to reach us: usa / europe / locations not listed : motorola literature distribution; p.o. box 5405, denver, colorado 80217. 13036752140 or 18004412447 japan : motorola japan ltd.; sps, technical information center, 3201, minamiaz abu. minatoku, tokyo 1068573 japan. 8 1334403569 asia / pacific : motorola semiconductors h.k. ltd.; silicon harbour centre, 2 dai king street, tai po industrial estate, tai po, n.t., hong ko ng. 85226668334 technical information center: 18005216274 home page : http://www.motorola.com/semiconductors/ MPC9990/d ?

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